Recently, the speed of MISFET has been increased mainly through micronization of the gate length and the like. However, shortened gate length, i.e., shortened channel length, causes phenomena such as reduction in a threshold value so called a short channel effect and deterioration (increase) of S-value that is an index of slope in a current-voltage characteristic of a sub-threshold area. In order to suppress the short channel effect, various techniques for increasing the mobility have been investigated since the mobility of carries is deteriorated when an impurity concentration in the channel area is increased.
As a way of example, there is disclosed a technique which uses germanium as described in the following. The carrier mobility of germanium is about 2.6 times as high in electrons and about 4.2 times as high in positive holes compared to the case of silicon. Therefore, such technique has drawn an attention as a future-generation technique.
For example, Non-Patent Document 1 discloses to form MISFET on a germanium substrate 101 as shown in FIG. 8. In FIG. 8, a p-type well 112 is formed on the p-type germanium substrate 101, and a gate insulating film 106 and a gate electrode 107 are formed thereon. N-type impurity diffusion regions 109 are formed by diffusing n-type impurities into the p-type well 112 to configure source/drain, and the n-type impurity diffusion regions 109 are provided by being isolated from each other while partially overlapping with both ends of the gate insulating film. Reference numeral 108 is a sidewall insulating film.
Further, Non-Patent Document 2 discloses to form a channel region by performing epitaxial growth of a germanium layer 103 on a silicon substrate 102 as shown in FIG. 9. In FIG. 9, a p-type well 112 is formed on the p-type silicon substrate 102. The germanium layer 103 is formed thereon by performing epitaxial growth, and a thin silicon layer 104 is further formed thereon. A gate insulating film 106 and a gate electrode 107 are formed on the silicon layer 104. N-type impurity diffusion regions 109 as a pair including a part of the germanium layer 103 and the silicon layer 104 are formed on the p-type well 112, while being isolated from each other by partially overlapping with both ends of the gate insulating film.
Non-Patent Document 1: H. Shang et al., “High Mobility p-channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric”, IEDM Technical Digest, pp. 441-444, December 2002.
Non-Patent Document 2: C. C. Yeo et al., “Electron Mobility Enhancement Using Ultrathin Pure Ge on Si Substrate”, IEEE Electron Device Letters, Vol. 26, No. 10, pp. 761-763, October 2005.